This invention relates generally to a circuit having a mixed topology of NPN transistors and a CMOS transistor controlled by an opamp to provide a substantially constant sinking current source.
Current-mode logic (CML) circuitry, such as shown in Colace, Electronic Product Design, January 1986, pages 43-46; Millman et al, xe2x80x9cPulse Digital, and Switching Waveformsxe2x80x9d, McGraw, Hill Book Company, New York, 1965, pages 358-359; and Hamilton et al xe2x80x9cBasic Integrated Circuit Engineeringxe2x80x9d, McGraw-Hill Book Company, New York, 1975, pages 492-497, offers high speed, but the required stacking of logic levels limits performance when low voltage supply operation is necessary.
Two common forms of CML that are used include a multi-level CML shown in prior art FIG. 1 and a single-ended version shown in prior art FIG. 2. The multi-level CML of FIG. 1 is differential, but requires different logic levels for inputs A, Abar and B, Bbar. Emitter followers can be used to translate from the top level to the bottom level as shown in FIG. 1.
The current-mode logic (CML), illustrated in FIG. 1, offers high speed, but the required stacking of logic levels limits performance. This performance limitation is especially noticeable when a low voltage supply operation is necessary.
The single-ended logic version shown in FIG. 2 operates with a reference voltage, V.sub.REF. This circuitry shows single-ended logic, which is much simpler, but the lack of differential signal paths makes the logic more susceptible to noise, especially from the voltage supply. This problem is aggravated in the case of high-speed logic in which small signal-swings are required.
A two-differential input conventional current mode logic circuit used in high speed switching logic gates typically requires a supply voltage of at least 2.7 volts in order to perform its associated logic functions. The benefit of using CML is its fast response time resulting from its small differential voltage between differential outputs. Notwithstanding, if the differential pairs of transistors are to operate within a high speed-switching regime, there is a minimum voltage that the transistors require across their respective collectors and emitters in order to operate outside the saturation region. In a CML system, signaling output transistors are arranged and mutually connected as a differentiating pair, with a common current source connected to xe2x80x9c0xe2x80x9d potential or earth potential. The NPN current source that is typically used lessens available xe2x80x9chead-roomxe2x80x9d between the current source and the supply voltage and thereby increases the requirement for a high enough supply voltage.
An aspect of this invention satisfies a need for provding CML circuits that can operate with a minimum supply voltage of approximately 2.0 volts at 25xc2x0 C.
A conventional current source comprising an NPN transistor having a degeneration resistor coupled between the emitter of the NPN transistor and ground and having a feedback circuit comprising a low power opamp, generally requires a voltage of approximately 800 mV between the collector and emitter to ensure that the transistor will not operate in saturation. If the voltage drops to below 500 mV the base current required increases substantially thereby placing demands on the low-power opamp to provide the required current. Therefore, although an NPN current source of this type can operate with a voltage of above 500 mV and below 800 mV across its collector emitter, it is preferred to ensure that the voltage is at or above 800 mV at all times so that the transistor does not go into a soft saturation mode of operation.
The prior art circuit shown in FIG. 3 having only a resistor replacing a conventional current source attempts to provide a solution to lessening the supply voltage requirement of a CML circuit by obviating the requirement for providing the necessary voltage across the collector emitter of an NPN transistor in a sinking current source. With the elimination of the bipolar junction transistor, the supply voltage requirement is substantially lessened, however other unwanted limitations are introduced. The absence of an NPN transistor in this circuit lessens the maximum supply voltage level required by 0.5 to 0.8 volts, however as the supply voltage increases, the current flowing through the circuit increases and the voltage difference between the differential transistor pairs increases; furthermore, one of the transistors of the differential pair goes into saturation due to the increased voltage across its respective load resistor. Operation in saturation results in a lower speed device.
In view of this, it is desired to have a current source that ensures a fixed amount of current, within predetermined limits while, requiring less voltage than conventional NPN current sources require.
In addition to CML circuits, this invention can be used to manufacture an analog signal mixer with a lower supply voltage than has customarily been provided.
It is an object of this invention to provide a CML circuit having at least a first pair of BJT differential transistors serially coupled to at least one of a second pair of BJT differential transistors, and wherein the supply voltage level required is below or substantially about 2.3 volts.
It is an object of this invention to provide a controller for ensuring a substantially constant current source for operation of a CML circuit.
An embodiment of the present invention is directed to logic circuitry which comprises a multiple input stage having a plurality of BJT gates disposed serially coupled to a common CMOS current source.
In accordance with the invention, there is provided, a current mode BiCMOS circuit comprising: an input stage having a plurality of electrically coupled NPN bipolar junction transistors coupled with a sinking current source having an NMOS transistor having a source terminal coupled to a ground terminal through a load resistor; and, an op-amp for controlling the NMOS transistor to ensure a substantially constant current source.
In particular, the circuitry of the present invention may comprise a number NPN input transistors coupled to and NMOS current source having a feedback circuit for ensuring a current passing therethrough is substantially non-varying.